MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 53

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDHX #opr
LDHX opr
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP
NSA
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
PSHA
PSHH
PSHX
Source
Form
Jump to Subroutine
Load A from M
Load H:X from M
Load X from M
Logical Shift Left
(Same as ASL)
Logical Shift Right
Move
Unsigned multiply
Negate (Two’s Complement)
No Operation
Nibble Swap A
Inclusive OR A and M
Push A onto Stack
Push H onto Stack
Push X onto Stack
Jump
Operation
Table 4-1. Instruction Set Summary (Sheet 4 of 6)
MC68HC908JW32 Data Sheet, Rev. 6
PC ← (PC) + n (n = 1, 2, or 3)
H:X ← (H:X) + 1 (IX+D, DIX+)
PC ← Unconditional Address
Push (PCH); SP ← (SP) – 1
Push (PCL); SP ← (SP) – 1
0
C
(M)
Push (H); SP ← (SP) – 1
Push (A); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
PC ← Jump Address
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
A ← (A[3:0]:A[7:4])
Destination
b7
H:X ← (M:M + 1)
b7
X:A ← (X) × (A)
Description
A ← (A) | (M)
A ← (M)
X ← (M)
None
← (M)
b0
b0
Source
C
0
V H I N Z C
– – – – – –
– – – – – –
0 – – ↕ ↕ –
0 – – ↕ ↕ – IMM
0 – – ↕ ↕ –
0 – – ↕ ↕ –
– 0 – – – 0 INH
– – – – – – INH
– – – – – – INH
0 – – ↕ ↕ –
– – – – – – INH
– – – – – – INH
– – – – – – INH
↕ – – ↕ ↕ ↕
↕ – – 0 ↕ ↕
↕ – – ↕ ↕ ↕
on CCR
Effect
Instruction Set Summary
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DD
DIX+
IMD
IX+D
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
9EDE
9EDA
9EE6
9ED6
9EEE
9EEA
9E68
9E64
9E60
BC
CC
DC
EC
BD
CD
DD
ED
CE
DE
CA
FC
FD
C6
D6
AE
BE
EE
FE
9D
AA
BA
DA
EA
A6
B6
E6
F6
45
55
38
48
58
68
78
34
44
54
64
74
4E
5E
6E
7E
42
30
40
50
60
70
62
FA
87
8B
89
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii jj
dd
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
ff
ff
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
53
2
3
4
3
2
4
5
6
5
4
2
3
4
4
3
2
4
5
3
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
5
4
4
4
5
4
1
1
4
3
5
1
3
2
3
4
4
3
2
4
5
2
2
2