MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 43

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

STOP — STOP Instruction Enable
COPD — COP Disable Bit
3.4 Configuration Register 2 (CONFIG2)
STOP_XCLKEN — Crystal Oscillator Stop Mode Enable
STOP_RCCLKEN — RC clock Stop Mode Enable
VREG33D — 3.3V USB Regulator Disable Bit
URSTD — USB Reset Disable Bit
Freescale Semiconductor
STOP enables the STOP instruction.
COPD disables the COP module. (See
Setting STOP_XCLKEN enables the external crystal (XTAL) oscillator to continue operating during
stop mode, in the other words, SIMOSCEN hold high during STOP mode. When this bit is cleared, the
external XTAL oscillator will be disabled during stop mode. Reset clears this bit.
Setting STOP_RCCLKEN enables the internal RC clock to continue operating during STOP mode.
When this bit is cleared, the internal RC clock will be disabled during STOP mode. Reset clears this bit.
VREG33D disables the USB 3.3V regulator completely.
URSTD disables the USB reset signal generating an internal reset to the CPU and internal registers.
Instead, it will generate an interrupt request to CPU.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
1 = XTAL oscillator enabled during stop mode
0 = XTAL oscillator disabled during stop mode
1 = Internal RC clock enabled during stop mode
0 = Internal RC clock disable during stop mode
1 = VREG33 regulator is disabled
0 = VREG33 regulator is enabled
1 = USB reset generates a interrupt request to CPU
0 = USB reset generates a chip reset
Address:
Reset:
Read:
Write:
$001D
Bit 7
0
Figure 3-3. Configuration Register 2 (CONFIG2)
= Unimplemented
6
0
MC68HC908JW32 Data Sheet, Rev. 6
XCLKEN
STOP_
Chapter 16 Computer Operating Properly
5
0
STOP_RC
CLKEN
4
0
†† Reset by POR only.
3
0
R
2
0
Configuration Register 2 (CONFIG2)
VREG33D
1
0
(COP).)
URSTD
Bit 0
0
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