MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 188

IC MCU 32K FLASH 8MHZ 48-LQFP

MCHC908JW32FAE

Manufacturer Part Number
MCHC908JW32FAE
Description
IC MCU 32K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCHC908JW32FAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, USB
Peripherals
LED, LVD, POR, PWM
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
48
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
HC08JW
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USB
Number Of Programmable I/os
29
Number Of Timers
2
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

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External Interrupt (IRQ)
14.5 PTE3/D– Pin
The PTE3 pin is configured as an interrupt input to trigger the IRQ interrupt when the following conditions
are satisfied:
Setting PTE3IE configures the PTE3 pin to an input pin with an internal pullup device. The PTE3 interrupt
is "ORed" with the IRQ input to trigger the IRQ interrupt
register affects both the IRQ pin and the PTE pin. An interrupt on PTE3 also sets the PTE3 interrupt flag,
PTE3IF, in the IRQ option control register (IOCR).
14.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can be cleared during the break
state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during
the break state. (See
To allow software to clear the IRQIRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a
latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), writing to the ACK bit in the IRQ status and control register during the break state has no
effect on the IRQ latch.
14.7 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR
has the following functions:
IRQF — IRQ Flag
188
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
The USB module is disabled
PTE3 pin configured for external interrupt input (PTE3IE = 1)
Shows the state of the IRQ flag
Clears the IRQ latch
Masks IRQ interrupt request
Controls triggering sensitivity of the IRQ pin
Address:
Reset:
Read:
Write:
Chapter 6 System Integration Module
$001E
Bit 7
Figure 14-3. IRQ Status and Control Register (ISCR)
0
0
= Unimplemented
6
0
0
MC68HC908JW32 Data Sheet, Rev. 6
5
0
0
4
0
0
Figure
IRQF
(SIM).)
3
0
14-1. Therefore, the IRQ status and control
ACK
2
0
0
IMASK
1
0
Freescale Semiconductor
MODE
Bit 0
0

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