MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 142

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Serial Peripheral Interface Module (SPI)
10.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It
is internally connected to V
10.13 I/O Registers
Three registers control and monitor SPI operation:
10.13.1 SPI Control Register
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
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This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit.
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
Figure 10-4
identical CPOL values. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
Figure 10-4
identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1
between bytes. (See
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
Enables SPI module interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
Address:
and
and
Reset:
Read:
Write:
Figure
Figure
SPRIE
$004C
Bit 7
Figure
R
0
10-6.) To transmit data between SPI modules, the SPI modules must have
10-6.) To transmit data between SPI modules, the SPI modules must have
SS
Figure 10-13. SPI Control Register (SPCR)
as shown in
= Reserved
10-12.) Reset sets the CPHA bit.
R
6
0
MC68HC908JW32 Data Sheet, Rev. 6
SPMSTR
5
1
Table
10-1.
CPOL
4
0
CPHA
3
1
SPWOM
2
0
SPE
1
0
Freescale Semiconductor
SPTIE
Bit 0
0