MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 75

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 6
System Integration Module (SIM)
6.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all
MCU activities. A block diagram of the SIM is shown in
input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
Table 6-1
Freescale Semiconductor
•
•
•
•
Bus clock generation and control for CPU and peripherals:
–
–
Master reset control, including power-on reset (POR) and COP timeout
Interrupt control:
–
–
–
CPU enable/disable timing
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
PORRST
shows the internal signal names used in this section.
Stop/wait/reset/break entry and recovery
Internal clock control
Acknowledge timing
Arbitration control timing
Vector address generation
ICLK
IRST
R/W
IDB
IAB
Internal RC oscillator clock
Selected oscillator clock from oscillator module
PLL VCO output and the divided PLL output
CGMVCLK-based or oscillator-based clock output from CGM module
(Bus clock = CGMOUT ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Table 6-1. Signal Name Conventions
MC68HC908JW32 Data Sheet, Rev. 6
Figure
Description
6-1.
Figure 6-2
is a summary of the SIM
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