HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 322

• Manufacturer Part Number: HD64F3644PV
• Description: IC H8/3644 MCU FLASH 32K 64SDIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644PV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Serial Communication Interface
Serial Status Register (SSR)
Note:
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,
RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, watch, subactive, or subsleep mode.
Bit 7 Transmit Data Register Empty (TDRE): Bit 7 indicates that transmit data has been
transferred from TDR to TSR.
Bit 7: TDRE
0
1
Rev. 6.00 Sep 12, 2006 page 300 of 526
REJ09B0326-0600
Bit
Initial value
Read/Write
* Only a write of 0 for flag clearing is possible.
R/(W) *
TDRE
Description
Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
Transmit data has not been written to TDR, or transmit data written in TDR has
been transferred to TSR
Setting conditions:
7
1
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR
R/(W) *
RDRF
0
6
R/(W) *
OER
5
0
R/(W) *
FER
4
0
R/(W) *
PER
3
0
TEND
R
2
1
MPBR
R
1
0
(initial value)
MPBT
R/W
0
0