HD64F3644PV Renesas Electronics America, HD64F3644PV Datasheet - Page 486

• Manufacturer Part Number: HD64F3644PV
• Description: IC H8/3644 MCU FLASH 32K 64SDIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644PV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix B Internal I/O Registers
SSR—Serial status register
Rev. 6.00 Sep 12, 2006 page 464 of 526
REJ09B0326-0600
Bit
Initial value
Read/Write
Note: * Only a write of 0 for flag clearing is possible.
Transmit data register empty
0
1
Receive data register full
0
1
Overrun error
Transmit data written in TDR has not been transferred to TSR
[Clearing conditions] • After reading TDRE = 1, cleared by writing 0 to TDRE
Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR
[Setting conditions]
0
1
There is no receive data in RDR
[Clearing conditions] • After reading RDRF = 1, cleared by writing 0 to RDRF
There is receive data in RDR
[Setting condition] When reception ends normally and receive data is transferred from RSR to RDR
Framing error
0
1
Reception in progress or completed
[Clearing condition] After reading OER = 1, cleared by writing 0 to OER
An overrun error has occurred during reception
[Setting condition] When the next serial reception is completed with RDRF set to 1
Parity error
0
1
Reception in progress or completed normally
[Clearing condition] After reading FER = 1, cleared by writing 0 to FER
A framing error has occurred during reception
[Setting condition]
Transmit end
0
1
Multiprocessor bit receive
Reception in progress or completed normally
[Clearing condition] After reading PER = 1, cleared by writing 0 to PER
A parity error has occurred during reception
[Setting condition]
TDRE
R/(W)
0
1
Transmission in progress
[Clearing conditions]
Transmission ended
[Setting conditions]
Multiprocessor bit transfer
7
1
0
1
• When data is written to TDR by an instruction
• When bit TE in serial control register 3 (SCR3) is cleared to 0
• When data is transferred from TDR to TSR
Data in which the multiprocessor bit is 0 has been received
Data in which the multiprocessor bit is 1 has been received
*
• When RDR data is read by an instruction
A 0 multiprocessor bit is transmitted
A 1 multiprocessor bit is transmitted
RDRF
R/(W)
When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
6
0
When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM) in the serial mode register (SMR)
*
• After reading TDRE = 1, cleared by writing 0 to TDRE
• When data is written to TDR by an instruction
• When bit TE in serial control register 3 (SCR3) is cleared to 0
• When bit TDRE is set to 1 when the last bit of a transmit character is sent
R/(W)
OER
5
0
*
R/(W)
FER
4
0
*
R/(W)
PER
3
0
*
H'FFAC
TEND
R
2
1
MPBR
R
1
0
MPBT
R/W
0
0
SCI3