UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 151

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

(2) Watchdog timer enable register (WDTE)
Address: FF49H
Symbol
WDTE
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH.
Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values.
Remarks 1. f
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated.
7
After reset: 9AH
2. After reset is released, WDTM can be written only once by an 8-bit memory
3. WDTM cannot be set by a 1-bit memory manipulation instruction.
4. When using the flash memory programming by self programming, set the overflow
2. f
3. ×:
4. Figures in parentheses apply to operation at f
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
Figure 9-3. Format of Watchdog Timer Enable Register (WDTE)
RL
X
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated. However, at the first write, if “1” and “x” are set for WDCS4 and
WDCS3 respectively and the watchdog timer is stopped, then the internal reset
signal does not occur even if the following are executed.
time for the watchdog timer so that enough overflow time is secured (Example 1-
byte writing: 200
signal is generated.
• Second write to WDTM
• 1-bit memory manipulation instruction to WDTE
• Writing of a value other than “ACH” to WDTE
:
: Low-speed internal oscillation clock oscillation frequency
6
System clock oscillation frequency
Don’t care
R/W
5
CHAPTER 9 WATCHDOG TIMER
µ
User’s Manual U16898EJ5V0UD
s MIN., 1-block deletion: 10 ms MIN.).
4
3
RL
= 480 kHz (MAX.), f
2
1
X
= 10 MHz.
0
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