UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 34

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

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(3) Stack pointer (SP)
SP
SP
(d) Carry flag (CY)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area (Other than the internal high-speed RAM area cannot be set as the stack
area).
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-8 and 3-9.
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the
SP15
SP _ 2
SP _ 2
SP _ 1
15
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It
stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit
operation instruction execution.
SP
SP14
2. Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits
SP before using the stack memory.
can be actually set.
Thus, if the stack pointer is specified to 0FF00H, it is converted to 0FB00H in the high-
speed RAM area, since 0FF00H is in the SFR area and not in the high-speed RAM area.
When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to
become 0FAFFH, but since that value is not in the high-speed RAM area, it is converted
to 0FEFFH, which is the same value as when 0FF00H is set to the stack pointer.
SP13 SP12 SP11 SP10 SP9
Lower half
register pairs
Upper half
register pairs
PUSH rp
instruction
Figure 3-8. Data to Be Saved to Stack Memory
Figure 3-7. Stack Pointer Configuration
SP
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U16898EJ5V0UD
SP _ 2
SP _ 2
SP _ 1
SP
SP8
PC15 to PC8
CALL, CALLT
instructions
PC7 to PC0
SP7
SP6
SP5
SP
SP4
SP _ 3
SP _ 3
SP _ 2
SP _ 1
SP
SP3
SP2
PC15 to PC8
PC7 to PC0
SP1
Interrupt
PSW
SP0
0