UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 218

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

218
Maskable
Reset
Interrupt Type
Notes 1. Priority is the vector interrupt servicing priority order when several maskable interrupt requests are
Caution No interrupt sources correspond to the vector table address 0014H.
2. Basic configuration types (A) and (B) correspond to (A) and (B) in Figure 12-1.
3. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 0 is selected.
4. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 1 is selected.
generated at the same time. 1 is the highest and 13 is the lowest.
Priority
10
11
12
13
1
2
3
4
5
6
7
8
9
−
Note 1
INTLVI
INTP0
INTP1
INTTMH1
INTTM000
INTTM010
INTAD
INTP2
INTP3
INTTM80
INTSRE6
INTSR6
INTST6
RESET
POC
LVI
WDT
Name
CHAPTER 12 INTERRUPT FUNCTIONS
Table 12-1. Interrupt Sources
Low-voltage detection
Pin input edge detection
Match between TMH1 and CMP01
Match between TM00 and CR000
(when compare register is specified),
TI010 pin valid edge detection (when
capture register is specified)
Match between TM00 and CR010
(when compare register is specified),
TI000 pin valid edge detection (when
capture register is specified)
End of A/D conversion
Pin input edge detection
Match between TM80 and CR80
UART6 reception error occurrence
End of UART6 reception
End of UART6 transmission
Reset input
Power-on-clear
Low-voltage detection
WDT overflow
User’s Manual U16898EJ5V0UD
Interrupt Source
Trigger
Note 3
Note 4
Internal
External
Internal
External
Internal
Internal/
External
−
Vector Table
Address
000AH
000CH
000EH
001CH
0006H
0008H
0010H
0012H
0016H
0018H
001AH
001EH
0020H
0000H
Configuration
Type
Basic
(A)
(B)
(A)
(B)
(A)
−
Note 2