UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 88

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

88
(3) 16-bit capture/compare register 010 (CR010)
CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control
register 00 (CRC00).
CR010 is set by 16-bit memory manipulation instruction.
Reset signal generation clears CR010 to 0000H.
• When CR010 is used as a compare register
• When CR010 is used as a capture register
Remarks 1. Setting ES010, ES000 = 1, 0 is prohibited.
Cautions 1. In the free-running mode and in the clear & start mode using the valid edge of the TI000
Falling edge
Rising edge
Both rising and falling edges
The value set in CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an
interrupt request (INTTM010) is generated if they match.
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by
means of prescaler mode register 00 (PRM00) (refer to Table 6-3).
Address: FF16H, FF17H
Symbol
CR010
CR010 Capture Trigger
2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)
Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)
2. If the new value of CR010 is less than the value of 16-bit timer counter 0 (TM00), TM00
3. The value of CR010 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR010 set in compare mode even if a
5. If the register read period and the input of the capture trigger conflict when CR010 is
6. Changing the CR010 setting during TM00 operation may cause a malfunction. To change
Figure 6-4. Format of 16-bit Timer Capture/Compare Register 010 (CR010)
CRC002:
pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010
changes from 0000H to 0001H following overflow (FFFFH).
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR010 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR010 is changed.
capture trigger is input.
used as a capture register, the capture trigger input takes precedence and the read data
is undefined. Also, if the timer count stop and the input of the capture trigger conflict,
the capture data is undefined.
the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing
compare register during timer operation.
7
6
5
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
After reset: 0000H
Bit 2 of capture/compare control register 00 (CRC00)
FF17H
4
Falling edge
Rising edge
Both rising and falling edges
3
User’s Manual U16898EJ5V0UD
2
1
R/W
0
7
TI000 Pin Valid Edge
6
5
FF16H
4
3
ES010
1
0
0
2
1
ES000
0
0
1
1