UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 243

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

High-speed internal oscillation clock or
Notes 1.
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
Notes 1.
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remarks 1. f
Internal reset signal
Watchdog overflow
2.
2.
oscillation clock
Crystal/ceramic
(except P130)
effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.
2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
The operation stop time is 277
Set high level output using software.
The operation stop time is 276
Set high level output using software.
CPU clock
Internal reset signal
external clock input
Watchdog overflow
effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.
X
Port pin
Port pin
: System clock oscillation frequency
(P130)
(except P130)
<1> With high-speed internal oscillation clock or external clock input
CPU clock
Port pin
Port pin
(P130)
Figure 14-3. Timing of Reset by Overflow of Watchdog Timer
Normal operation
in progress
Normal operation
<2> With crystal/ceramic oscillation clock
in progress
CHAPTER 14 RESET FUNCTION
User’s Manual U16898EJ5V0UD
µ
µ
s (MIN.), 544
s (MIN.), 544
(oscillation stops)
Reset period
(oscillation stops)
µ
µ
Reset period
s (TYP.), and 1.075 ms (MAX.).
s (TYP.), and 1.074 ms (MAX.).
Oscillation stabilization
time (2
Operation stops because option
byte is referenced
10
/f
X
to 2
Hi-Z
17
/f
X
)
Operation stops because option
byte is referenced
Normal operation (reset processing, CPU clock)
Hi-Z
Normal operation
(reset processing, CPU clock)
Note 1
.
Note 1
.
Note 2
Note 2
243