UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 186

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

11.3 Registers Controlling Serial Interface UART6
(1) Asynchronous serial interface operation mode register 6 (ASIM6)
186
Address: FF90H After reset: 01H R/W
Serial interface UART6 is controlled by the following nine registers.
• Asynchronous serial interface operation mode register 6 (ASIM6)
• Asynchronous serial interface reception error status register 6 (ASIS6)
• Asynchronous serial interface transmission status register 6 (ASIF6)
• Clock selection register 6 (CKSR6)
• Baud rate generator control register 6 (BRGC6)
• Asynchronous serial interface control register 6 (ASICL6)
• Input switch control register (ISC)
• Port mode register 4 (PM4)
• Port register 4 (P4)
Notes 1.
Symbol
ASIM6
This 8-bit register controls the serial communication operations of serial interface UART6.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation
Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)
2.
3.
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
The output of the T
POWER6 is cleared to 0 during a transmission.
Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
A base clock (f
one clock of the base clock (f
POWER6
POWER6
0
1
<7>
Note 1
Note 3
Disable operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
Enable operation of the internal operation clock
TXE6
XCLK6
<6>
X
) is supplied as the internal operation clock when the POWER6 bit is set to 1 and
D6 pin goes high and the input from the R
CHAPTER 11 SERIAL INTERFACE UART6
RXE6
<5>
XCLK6
User’s Manual U16898EJ5V0UD
Enabling/disabling operation of internal operation clock
Note 2
) has elapsed.
.
PS61
4
PS60
3
X
D6 pin is fixed to the high level when
CL6
2
SL6
1
ISRM6
0