UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 81

8BIT MCU, 4K FLASH, 256B RAM, 78F9222

UPD78F9222MC(T)-5A4-A

Manufacturer Part Number
UPD78F9222MC(T)-5A4-A
Description
8BIT MCU, 4K FLASH, 256B RAM, 78F9222
Manufacturer
NEC
Datasheet

Specifications of UPD78F9222MC(T)-5A4-A

Controller Family/series
UPD78
No. Of I/o's
17
Ram Memory Size
256Byte
Cpu Speed
10MHz
No. Of Timers
4
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal

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Note Operation stop time is 277
(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
Remark PCC:
referenced after reset, and the system clock is selected.
system clock.
System clock
Internal reset
CPU clock
PPCC: Preprocessor clock control register
RESET
V
DD
Figure 5-13. Status Transition of Default Start by External Clock Input
Processor clock control register
H
Figure 5-12. Timing of Default Start by External Clock Input
Interrupt
(a)
HALT
µ
System clock is selected.
s (MIN.), 544
CHAPTER 5 CLOCK GENERATORS
(Operation stops
selected by option byte
Option byte is read.
External clock input
Clock division ratio
instruction
variable during
power-on-clear
CPU operation
HALT
User’s Manual U16898EJ5V0UD
Reset by
application
Power
µ
V
Start with PCC = 02H,
PPCC = 02H
Note
instruction
s (TYP.), and 1.075 ms (MAX.).
DD
STOP
)
> 2.1 V (TYP.)
(b)
STOP
Interrupt
PCC = 02H, PPCC = 02H
Reset signal
External clock input
81

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