UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 400

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

400
Flash
memory
Function
Self
programming
function
FLPMC: Flash
programming
mode control
register
PFCMD: Flash
protect
command
register
PFS: Flash
status register
FLAPH,
FLAPL: Flash
address
pointers H and
L
FLAPHC,
FLAPLC: Flash
address pointer
H/L compare
registers
Details of
Function
Check FPRERR using a 1-bit memory manipulation instruction.
Since the security function set via on-board/off-board programming is disabled
in self programming mode, the self programming command can be executed
regardless of the security function setting. To disable write or erase processing
during self programming, set the protect byte.
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash
address pointer H compare register (FLAPHC) to 0 before executing the self
programming command. If the self programming command is executed with
these bits set to 1, the device may malfunction.
Clear the value of the FLCMD register to 00H immediately before setting to self
programming mode and normal mode.
For cautions in case of setting the self programming mode, refer to 18.8.2
Cautions on self programming function.
Set the CPU clock beforehand so that it is 1 MHz or higher during self
programming.
Execute self programming after executing the NOP and HALT instructions
immediately after executing a specific sequence to set self programming mode.
At this time, the HALT instruction is automatically released after 10
2 CPU clocks (f
If the clock of the oscillator or an external clock is selected as the system clock,
execute the NOP and HALT instructions immediately after executing a specific
sequence to set self programming mode, wait for 8
status, and then execute self programming.
Clear the value of the FLCMD register to 00H immediately before setting to self
programming mode and normal mode.
Interrupt servicing cannot be executed in self programming mode. Disable
interrupt servicing (by executing the DI instruction while MK0 = FFH) between
the points before executing the specific sequence that sets self programming
mode and after executing the specific sequence that changes the mode to the
normal mode.
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash
address pointer H compare register (FLAPHC) to 0 before executing the self
programming command. If the self programming command is executed with
these bits set to 1, the device may malfunction.
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash
address pointer H compare register (FLAPHC) to 0 before executing the self
programming command. If the self programming command is executed with
these bits set to 1, the device may malfunction.
Set the number of the block subject to a block erase, verify, or blank check
(same value as FLAPH) to FLAPHC.
Clear FLAPLC to 00H when a block erase is performed, and FFH when a blank
check is performed.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16898EJ5V0UD
CPU
).
Cautions
µ
s after releasing the HALT
µ
s (MAX.) +
p. 279
p. 279
p. 279
p. 280
p. 280
p. 280
p. 280
p. 280
p. 281
p. 281
p. 284
p. 284
p. 284
p. 284
Page
(17/19)