UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 253

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

16.3 Registers Controlling Low-Voltage Detector
(1) Low-voltage detect register (LVIM)
The low-voltage detector is controlled by the following registers.
• Low-voltage detect register (LVIM)
• Low-voltage detection level select register (LVIS)
Address: FF50H
Symbol
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H
LVIM
Notes 1.
Cautions 1. To stop LVI, follow either of the procedures below.
LVION
LVIF
LVION
LVIMD
<7>
0
1
0
1
0
1
Note 4
2.
3.
4.
Note 3
After reset: 00H
2. Be sure to set bits 2 to 6 to 0.
For a reset by LVI, the value of LVIM is not initialized.
Bit 0 is a read-only bit.
When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is
confirmed at LVIF.
The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
Disable operation
Enable operation
Generate interrupt signal when supply voltage (V
Generate internal reset signal when supply voltage (V
Supply voltage (V
Supply voltage (V
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
Figure 16-2. Format of Low-Voltage Detect Register (LVIM)
6
0
Note 1
CHAPTER 16 LOW-VOLTAGE DETECTOR
5
0
DD
DD
Note 1
R/W
) ≥ detection voltage (V
) < detection voltage (V
Low-voltage detection operation mode selection
.
User’s Manual U16898EJ5V0UD
Note 2
Enabling low-voltage detection operation
4
0
Low-voltage detection flag
LVI
LVI
3
0
), or when operation is disabled
)
DD
) < detection voltage (V
DD
) < detection voltage (V
2
0
LVIMD
<1>
LVI
)
LVI
LVIF
)
<0>
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