UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 330

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

20.2 Operation List
330
MOV
XCH
Mnemonic
Notes 1. Except r = A.
Remark
2. Except r = A, X.
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, X
A, r
A, saddr
A, sfr
A, [DE]
A, [HL]
A, [HL, byte]
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
Operand
Note 1
Note 1
Note 2
CHAPTER 20 INSTRUCTION SET OVERVIEW
Bytes
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
User’s Manual U16898EJ5V0UD
Clocks
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
(saddr) ← A
r ← byte
(saddr) ← byte
sfr ← byte
A ← r
r ← A
A ← (saddr)
A ← sfr
sfr ← A
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
(HL) ← A
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
A ↔ r
A ↔ (saddr)
A ↔ sfr
A ↔ (DE)
A ↔ (HL)
A ↔ (HL + byte)
CPU
) selected by the processor clock control
Operation
Z
×
×
Flag
AC CY
×
×
×
×