UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 334

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

334
CALL
CALLT
RET
RETI
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
BT
BF
DBNZ
NOP
EI
DI
HALT
STOP
Mnemonic
Remark
!addr16
[addr5]
PSW
rp
PSW
rp
SP, AX
AX, SP
!addr16
$addr16
AX
$saddr16
$saddr16
$saddr16
$saddr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
C, $addr16
saddr, $addr16
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
Operand
CHAPTER 20 INSTRUCTION SET OVERVIEW
Bytes
3
1
1
1
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
1
3
3
1
1
User’s Manual U16898EJ5V0UD
Clocks
10
10
10
10
10
10
6
8
6
8
2
4
4
6
8
6
6
6
6
6
6
6
6
8
8
6
6
8
2
6
6
2
2
(saddr) ← (saddr) − 1, then
(SP − 1) ← (PC + 3)
PC ← addr16, SP ← SP − 2
(SP − 1) ← (PC + 1)
PC
PC
PC
PC
SP ← SP + 3
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rp
PSW ← (SP), SP ← SP + 1
rp
SP ← AX
AX ← SP
PC ← addr16
PC ← PC + 2 + jdisp8
PC
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
No Operation
IE ← 1 (Enable Interrupt)
IE ← 0 (Disable Interrupt)
Set HALT Mode
Set STOP Mode
H
H
L
H
H
H
← (SP + 1), rp
← (00000000, addr5), SP ← SP − 2
← (00000000, addr5 + 1),
← (SP + 1), PC
← (SP + 1), PC
← A, PC
L
H
CPU
, (SP − 2) ← rp
← X
) selected by the processor clock control
L
← (SP), SP ← SP + 2
H
H
L
L
Operation
, (SP − 2) ← (PC + 3)
, (SP − 2) ← (PC + 1)
← (SP), SP ← SP + 2
← (SP), PSW ← (SP + 2),
L
, SP ← SP − 2
L
L
,
,
Z
R
R
Flag
AC CY
R
R
R
R