UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 331

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

MOVW
XCHW
ADD
ADDC
SUB
Mnemonic
Note Only when rp = BC, DE, or HL.
Remark
rp, #word
AX, saddrp
saddrp, AX
AX, rp
rp, AX
AX, rp
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
Operand
Note
Note
Note
CHAPTER 20 INSTRUCTION SET OVERVIEW
Bytes
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
User’s Manual U16898EJ5V0UD
Clocks
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
rp ← word
AX ← (saddrp)
(saddrp) ← AX
AX ← rp
rp ← AX
AX ↔ rp
(saddr), CY ← (saddr) + byte
A, CY ← A + r
A, CY ← A + (HL)
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
A, CY ← A + (HL) + CY
(saddr), CY ← (saddr) − byte
A, CY ← A − r
A, CY ← A − (HL)
A, CY ← A + byte
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL + byte)
CPU
) selected by the processor clock control
Operation
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
331
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×