UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 90

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

90
Address: FF60H
Symbol
TMC00
TMC003 TMC002 TMC001
OVF00
Cautions 1. The timer operation must be stopped before writing to bits other than the OVF00 flag.
Remark TM00:
0
1
0
0
0
0
1
1
1
1
Overflow not detected
Overflow detected
7
0
0
0
1
1
0
0
1
1
CR000: 16-bit timer capture/compare register 000
CR010: 16-bit timer capture/compare register 010
2. If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is
3. Except when the valid edge of the TI000 pin is selected as the count clock, stop the timer
4. Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 (PRM00)
5. If the clear & start mode entered on a match between TM00 and CR000, clear & start mode at
6. Even if the OVF00 flag is cleared before the next count clock is counted (before TM00
7. The capture operation is performed at the fall of the count clock. An interrupt request input
6
0
input to the TI000/TI010 pins.
operation before setting STOP mode or system clock stop mode; otherwise the timer may
malfunction when the system clock starts.
after stopping the timer operation.
the valid edge of the TI000 pin, or free-running mode is selected, when the set value of CR000
is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1.
becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and
clear is disabled.
(INTTM0n0), however, occurs at the rise of the next count clock.
After reset: 00H
Figure 6-5. Format of 16-bit Timer Mode Control Register 00 (TMC00)
0
1
0
1
0
1
0
1
16-bit timer counter 00
5
0
Operation stop
(TM00 cleared to 0)
Free-running mode
Clear & start occurs on valid
edge of TI000 pin
Clear & start occurs on match
between TM00 and CR000
4
0
Operating mode and clear
TMC003
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
mode selection
R/W
3
TMC002
Overflow detection of 16-bit timer counter 00 (TM00)
2
User’s Manual U16898EJ5V0UD
TMC001
1
OVF00
<0>
No change
Match between TM00 and
CR000 or match between
TM00 and CR010
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
Match between TM00 and
CR000 or match between
TM00 and CR010
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
TO00 inversion timing selection
−
Not generated
<When operating as compare
register>
Generated on match between
TM00 and CR000, or match
between TM00 and CR010
<When operating as capture
register>
Generated on TI000 pin and
TI010 pin valid edge
Interrupt request generation