PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 213

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

18.4
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the TXx pin (RC6/TX1/CK1 or RG1/TX2/CK2), instead
of being supplied internally in Master mode. TRISC<6>
must be set for this mode. This allows the device to
transfer or receive data while in Sleep mode. Slave
mode is entered by clearing bit CSRC (TXSTAx<7>).
18.4.1
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
 2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
TXREGx
TXSTAx
SPBRGx
Legend:
Note 1:
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXxIF will not be set.
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit TXxIF will now be
set.
If enable bit TXxIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
(1)
(1)
(1)
(1)
USART Synchronous Slave Mode
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
USART SYNCHRONOUS SLAVE
TRANSMIT
USART Transmit Register
Baud Rate Generator Register
PSPIF
PSPIE
PSPIP
CSRC
SPEN
GIEH
Bit 7
GIE/
—
—
—
PIC18F6520/8520/6620/8620/6720/8720
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
—
—
—
TMR0IE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TXEN
Bit 5
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
SYNC
Bit 4
TMR4IF
TMR4IE
TMR4IP
ADDEN
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
CCP5IF
CCP5IE
CCP5IP
BRGH
FERR
Bit 2
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXxIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR2IE
TMR2IP
TMR2IF
CCP4IF
CCP4IE
CCP4IP
INT0IF
OERR
TRMT
Bit 1
TMR1IF
TMR1IE
TMR1IP
CCP3IE
CCP3IP
CCP3IF
RX9D
TX9D
RBIF
Bit 0
0000 0000
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on
DS39609B-page 211
0000 0000
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
Value on
all other
Resets