PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 45

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 4-2:
FIGURE 4-3:
4.2.3
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program
execution, is a desirable option. To push the current PC
value onto the stack, a PUSH instruction can be
executed. This will increment the stack pointer and load
the current PC value onto the stack. TOSU, TOSH and
TOSL can then be modified to place a return address
on the stack.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP
instruction discards the current TOS by decrementing
the stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4-0
PUSH AND POP INSTRUCTIONS
PIC18F6520/8520/6620/8620/6720/8720
TOSU
STKPTR REGISTER
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
0x00
STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
Unimplemented: Read as ‘0’
SP4:SP0: Stack Pointer Location bits
Legend:
R = Readable bit
- n = Value at POR
bit 7
STKFUL
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
R/C-0
(1)
TOSH
STKUNF
0x1A
R/C-0
(1)
Top-of-Stack
TOSL
0x34
W = Writable bit
‘1’ = Bit is set
U-0
—
Return Address Stack
R/W-0
0x001A34
0x000D58
4.2.4
These Resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the
appropriate STKFUL or STKUNF bit, but not cause a
device Reset. When the STVREN bit is enabled, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR Reset.
SP4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
STACK FULL/UNDERFLOW RESETS
11111
11110
11101
00011
00010
00001
00000
SP3
STKPTR<4:0>
R/W-0
00010
SP2
x = Bit is unknown
R/W-0
SP1
DS39609B-page 43
R/W-0
SP0
bit 0