PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 368

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F6520/8520/6620/8620/6720/8720
BN .................................................................................... 268
BNC .................................................................................. 269
BNN .................................................................................. 269
BNOV ............................................................................... 270
BNZ .................................................................................. 270
BOR. See Brown-out Reset.
BOV .................................................................................. 273
BRA .................................................................................. 271
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ..................................................... 30
BSF .................................................................................. 271
BTFSC ............................................................................. 272
BTFSS .............................................................................. 272
BTG .................................................................................. 273
BZ ..................................................................................... 274
C
C Compilers
CALL ................................................................................ 274
Capture (CCP Module) ..................................................... 151
Capture/Compare/PWM (CCP) ........................................ 149
Capture/Compare/PWM Requirements
CLKO and I/O Timing Requirements ....................... 324, 325
Clocking Scheme/Instruction Cycle .................................... 44
CLRF ................................................................................ 275
CLRWDT .......................................................................... 275
Code Examples
DS39609B-page 366
USART Transmit ...................................................... 204
Voltage Reference Output Buffer Example .............. 231
Watchdog Timer ....................................................... 251
MPLAB C17 ............................................................. 302
MPLAB C18 ............................................................. 302
MPLAB C30 ............................................................. 302
Associated Registers ............................................... 153
CCP Pin Configuration ............................................. 151
CCPR1H:CCPR1L Registers ................................... 151
Software Interrupt .................................................... 151
Timer1/Timer3 Mode Selection ................................ 151
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 150
CCPRxH Register .................................................... 150
CCPRxL Register ..................................................... 150
Compare Mode. See Compare.
Interconnect Configurations ..................................... 150
Module Configuration ............................................... 150
PWM Mode. See PWM.
(All CCP Modules) ................................................... 329
16 x 16 Signed Multiply Routine ................................ 86
16 x 16 Unsigned Multiply Routine ............................ 86
8 x 8 Signed Multiply Routine .................................... 85
8 x 8 Unsigned Multiply Routine ................................ 85
Changing Between Capture Prescalers ................... 151
Data EEPROM Read ................................................. 81
Data EEPROM Refresh Routine ................................ 82
Data EEPROM Write ................................................. 81
Erasing a Flash Program Memory Row ..................... 66
Fast Register Stack .................................................... 44
How to Clear RAM (Bank 1)
Implementing a Real-Time Clock Using a
Initializing PORTA .................................................... 103
Initializing PORTB .................................................... 106
Initializing PORTC .................................................... 109
Initializing PORTD .................................................... 111
Initializing PORTE .................................................... 114
Using Indirect Addressing .................................. 57
Timer1 Interrupt Service .................................. 139
Code Protection ............................................................... 239
COMF .............................................................................. 276
Comparator ...................................................................... 223
Comparator Specifications ............................................... 317
Comparator Voltage Reference ....................................... 229
Compare (CCP Module) .................................................. 152
Compare (CCP2 Module)
Configuration Bits ............................................................ 239
Context Saving During Interrupts ..................................... 102
Control Registers
Conversion Considerations .............................................. 362
CPFSEQ .......................................................................... 276
CPFSGT .......................................................................... 277
CPFSLT ........................................................................... 277
D
Data EEPROM Memory
Initializing PORTF .................................................... 117
Initializing PORTG ................................................... 120
Initializing PORTH ................................................... 122
Initializing PORTJ .................................................... 125
Loading the SSPBUF (SSPSR) Register ................. 160
Reading a Flash Program Memory Word .................. 65
Saving Status, WREG and BSR Registers
Writing to Flash Program Memory ....................... 68–69
Analog Input Connection Considerations ................ 227
Associated Registers ............................................... 228
Configuration ........................................................... 224
Effects of a Reset .................................................... 227
Interrupts ................................................................. 226
Operation ................................................................. 225
Operation During Sleep ........................................... 227
Outputs .................................................................... 225
Reference ................................................................ 225
Response Time ........................................................ 225
Accuracy and Error .................................................. 230
Associated Registers ............................................... 231
Configuring .............................................................. 229
Connection Considerations ...................................... 230
Effects of a Reset .................................................... 230
Operation During Sleep ........................................... 230
Associated Registers ............................................... 153
CCP Pin Configuration ............................................. 152
CCPR1 Register ...................................................... 152
Software Interrupt .................................................... 152
Special Event Trigger .............................. 138, 145, 152
Timer1/Timer3 Mode Selection ................................ 152
Special Event Trigger .............................................. 220
EECON1 and EECON2 ............................................. 62
TABLAT (Table Latch) Register ................................. 64
TBLPTR (Table Pointer) Register .............................. 64
Associated Registers ................................................. 83
EEADR Register ........................................................ 79
EEADRH Register ..................................................... 79
EECON1 Register ...................................................... 79
EECON2 Register ...................................................... 79
Operation During Code-Protect ................................. 82
Protection Against Spurious Write ............................. 82
Reading ..................................................................... 81
Using ......................................................................... 82
Write Verify ................................................................ 82
Writing ....................................................................... 81
in RAM ............................................................. 102
External Signal ................................................ 225
Internal Signal .................................................. 225
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