PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 276

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F6520/8520/6620/8620/6720/8720
BZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39609B-page 274
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Zero
If Zero
Q1
Q1
No
PC
PC
Read literal
Read literal
operation
Branch if Zero
[ label ] BZ
-128
if Zero bit is ‘1’
(PC) + 2 + 2n
None
If the Zero bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
1110
Q2
Q2
No
‘n’
‘n’
=
=
=
=
=
n
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
127
0000
BZ
operation
Process
Process
n
Data
Data
Q3
Q3
No
PC
Jump
nnnn
Write to PC
operation
operation
Q4
Q4
No
No
nnnn
CALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PC
TOS
WS
BSRS
STATUSS =
Q1
No
Read literal
=
=
=
=
=
operation
Subroutine Call
[ label ] CALL k [,s]
0
s
(PC) + 4
k
if s = 1
(W)
(STATUS)
(BSR)
None
Subroutine call of entire 2-Mbyte
memory range. First, return
address (PC+ 4) is pushed onto the
return stack. If ‘s’ = 1, the W,
Status and BSR registers are also
pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If ‘s’ = 0, no update
occurs (default). Then, the 20-bit
value ‘k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
2
2
HERE
‘k’<7:0>
1110
1111
Q2
No
address (HERE)
address (THERE)
address (HERE + 4)
W
BSR
STATUS
k
[0,1]
 2004 Microchip Technology Inc.
PC<20:1>,
WS,
1048575
BSRS
k
110s
CALL
19
Push PC to
TOS,
operation
kkk
STATUSS,
stack
Q3
No
THERE,1
k
kkkk
7
kkk
Read literal
Write to PC
‘k’<19:8>,
operation
Q4
No
kkkk
kkkk
0
8