PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 222

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F6520/8520/6620/8620/6720/8720
19.4
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D Result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2 T
is required before the next acquisition is started. After
this 2 T
automatically started.
FIGURE 19-3:
DS39609B-page 220
Note:
AD
A/D Conversions
T
CY
Set GO bit
wait, acquisition on the selected channel is
Holding capacitor is disconnected from analog input (typically 100 ns)
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
- T
AD
Conversion starts
T
AD
b9
A/D CONVERSION T
1 T
AD
b8
2 T
AD
b7
3 T
AD
b6
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
4 T
AD
AD
AD
b5
5 T
CYCLES
wait
ADIF bit is set, holding capacitor is connected to analog input.
AD
b4
6 T
AD
b3
7 T
19.5
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and
the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D module,
but will still reset the Timer1 (or Timer3) counter.
AD
b2
8
Use of the CCP2 Trigger
T
AD
b1
9 T
AD
b0
10
T
AD
 2004 Microchip Technology Inc.
b0
11