PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 217

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 19-3:
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(V
V
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
 2004 Microchip Technology Inc.
REF
DD
+ pin and RA2/AN2/V
and V
bit 7
bit 6-3
bit 2-0
SS
), or the voltage level on the RA3/AN3/
PIC18F6520/8520/6620/8620/6720/8720
ADCON2 REGISTER
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
Unimplemented: Read as ‘0’
ADCS1:ADCS0: A/D Conversion Clock Select bits
000 = F
001 = F
010 = F
011 = F
100 = F
101 = F
110 = F
111 = F
Legend:
R = Readable bit
- n = Value at POR
R/W-0
ADFM
REF
- pin.
OSC
OSC
OSC
RC
OSC
OSC
OSC
RC
(clock derived from an RC oscillator = 1 MHz max)
(clock derived from an RC oscillator = 1 MHz max)
/2
/8
/32
/4
/16
/64
U-0
—
U-0
—
W = Writable bit
‘1’ = Bit is set
U-0
—
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a
voltage reference), or as a digital I/O. The ADRESH
and ADRESL registers contain the result of the A/D
conversion. When the A/D conversion is complete, the
result is loaded into the ADRESH/ADRESL registers,
the GO/DONE bit (ADCON0 register) is cleared and
A/D interrupt flag bit, ADIF, is set. The block diagram of
the A/D module is shown in Figure 19-1.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
ADCS2
R/W-0
x = Bit is unknown
ADCS1
R/W-0
DS39609B-page 215
ADCS0
R/W-0
bit 0