PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 47
PIC18F8520-I/PT
Manufacturer Part Number
PIC18F8520-I/PT
Description
80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F8520-IPT.pdf
(380 pages)
Specifications of PIC18F8520-I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
68
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
80-pin TQFP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
40 MHz
Timers
2-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8520-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8520-I/PT
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4.6
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined, such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 4-2).
EXAMPLE 4-2:
4.7
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 4-5 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 4.4 “PCL,
PCLATH and PCLATU”).
The CALL and GOTO instructions have an absolute
program
instruction. Since instructions are always stored on
FIGURE 4-5:
2004 Microchip Technology Inc.
1. MOVLW 55h
2. MOVWF PORTB
3. BRA
4. BSF
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed”
from the pipeline, while the new instruction is being fetched and then executed.
Instruction Flow/Pipelining
Instructions in Program Memory
SUB_1
memory
PORTA, BIT3 (Forced NOP)
PIC18F6520/8520/6620/8620/6720/8720
Instruction 1:
Instruction 2:
Instruction 3:
address
INSTRUCTION PIPELINE FLOW
INSTRUCTIONS IN PROGRAM MEMORY
Fetch 1
embedded
T
Program Memory
Byte Locations
MOVLW
GOTO
MOVFF
CY
0
Execute 1
055h
000006h
123h, 456h
Fetch 2
into
T
CY
1
the
Execute 2
Fetch 3
T
CY
LSB =
2
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
word boundaries, the data contained in the instruction
is a word address. The word address is written to
PC<20:1>, which accesses the desired byte address in
program memory. Instruction #2 in Figure 4-5 shows
how the instruction “GOTO 000006h” is encoded in the
program memory. Program branch instructions, which
encode a relative address offset, operate in the same
manner. The offset value stored in a branch instruction
represents the number of single-word instructions that
the PC will be offset by. Section 24.0 “Instruction Set
Summary” provides further details of the instruction
set.
0Fh
EFh
F0h
C1h
F4h
1
Execute 3
Fetch 4
T
CY
LSB =
3
55h
03h
00h
23h
56h
0
Fetch SUB_1 Execute SUB_1
Flush (NOP)
Word Address
T
CY
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
4
DS39609B-page 45
T
CY
5
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