PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 113

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
ENSA…
PMOD…
XFS…
ECM…
SSD0…
Enable S
Only applicable if FMR1.XFS is set to one.
0…
1…
PCM Mode
For E1 application this bit must be set low. Switching from E1 to T1 or
vv the device needs up to 10 sec to settle up to the internal clocking.
FMR1.PMOD of all 4 channels has to be set equally.
0…
1…
Transmit Framing Select
Selection of the transmit framing format could be done independent
of the receive framing format.
0…
1…
Error Counter Mode
The function of the error counters will be determined by this bit.
0
1…
Select System Data Rate 0
FMR1.SSD0 and SIC1.SD1 define the data rate on the system
highway. Programming is done with SSD1/SSD0 in the following
table.
00…2.048 MBit/s
S
Doubleframe format enabled.
CRC4-multiframe format enabled.
Normal operation. The S
XSW.XY0…4 and written to bits RSW.RY0…4.
the registers XSA4-8. In addition, the received information will
be written to registers RSA4-8. Transmitting contents of
registers XSA4-8 will be disabled if one of time-slot 0
transparent modes is enabled (XSP.TT0 or TSWM.SA4-8).
PCM 30 or E1 mode.
PCM 24 or T1 mode.
Before reading an error counter the corresponding bit in the
Disable Error Counter register (DEC) has to be set. In 8 bit
access the low byte of the error counter should always be read
before the high byte. The error counters will be reset with the
rising edge of the corresponding bits in the DEC register.
Every second the error counter will be latched and then
automatically be reset. The latched error counter state should
be read within the next second. Reading the error counter
during updating should be avoided.
a
-bit register access. The S
a
-Bit Access via Register XSA4-8
113
a
-bit information will be taken from bits
a
-bit information will be taken from
Operational Description E1
PEB 22554
09.98