PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 71

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Additionally, if bit FMR3.EXTIW is set and the multiframesynchronous state could not be
achieved within the 400 msec after finding the primary basic framing, the A-bit will be
transmitted active high to the remote end until the multiframing is found.
Note: The A-bit may be processed via the system interface. Setting bit TSWM.TRA
S
Due to signaling procedures using the five S
CRC multiframe structure, three possibilities of access via the microprocessor are
implemented.
• The standard procedure allows reading/writing the S
• The advanced procedure, enabled via bit FMR1.ENSA, allows reading/writing the
• The extended access via the receive and transmit FIFOs of the signaling controller. In
– SA6-Bit Detection according to ETS 300233
Four consecutive received SA6-bits are checked on the by ETS 300233 defined SA6-bit
combinations. The QuadFALC will detect following fixed SA6-bit combinations:
SA61,SA62,SA63,SA64 = 1000; 1010; 1100; 1110; 1111. All other possible 4 bit
combinations are grouped to status “X”.
A valid SA6-bit combination must occur three times in a row. The corresponding status
bit in register RSA6S will be set. Register RSA6S is from type “Clear on Read”. With any
Semiconductor Group
a
further support. The S
S
A transmit or receive multiframe begin interrupt (ISR0.RMB or ISR1.XMB) is provided.
Registers RSA4-8 contains the service word information of the previously received
CRC-multiframe or 8 doubleframes (bitslots 4-8 of every service word). These
registers will be updated with every multiframe begin interrupt ISR0.RMB.
With the transmit multiframe begin an interrupt ISR1.XMB is generated and the
contents of this registers XSA4-8 will be copied into shadow registers. The contents
will subsequently sent out in the service words of the next outgoing CRC multiframe
(or every doubleframes) if none of the time-slot 0 transparent modes is enabled. The
transmit multiframe begin interrupt XMB request that these registers should be
serviced. If requests for new information will be ignored, current contents will be
repeated.
this mode it is possible to transmit / receive a HDLC frame or a transparent bit stream
in any combination of the S
the corresponding bits XC0.SA8E-4E / TSWM.TSA8-4 and resetting of registers
TTR1-4, RTR1-4 and FMR1.ENSA. The access to and from the FIFOs is supported
by ISR0.RME,RPF and ISR1.XPR,ALS.
- Bit Access
a
-bit registers RSA4 … 8, XSA4 … 8.
enables transparency for the A bit in transmit direction (refer to table 7).
a
-bit information will be updated every other frame.
a
bits. Enabling is done by setting of bit CCR1.EITS and
71
a
bits (S
a4
… S
a
-bit registers RSW, XSW without
a8
Functional Description E1
) of every other frame of the
PEB 22554
09.98