PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 253

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

• two errors within 4/5/6 framing bits
• two or more erroneous framing bits within one ESF multiframe
• more than 320 CRC6 errors per second interval (FMR5.SSC2)
• 4 incorrect (1 out of 6) consecutive multiframes independent of CRC6 errors.
There are four multiframe synchronization modes selectable via FMR2.MCSP and
FMR2.SSP.
• FMR2.MCSP/SSP = 00 : In the synchronous state, the setting of FMR0.FRS or
• FMR2.MCSP/SSP = 01: Synchronization is achieved when 3 consecutive multiframe
• FMR2.MCSP/SSP = 10: This mode has been added in order to be able to choose
• FMR2.MCSP/SSP = 11: Synchronization including automatic CRC6 checking
Semiconductor Group
FMR0.EXLS resets the synchronizer and initiates a new frame search. The
synchronous state will be reached again, if there is only one definite framing
candidate. In the case of repeated apparent simulated candidates, the synchronizer
remains in the asynchronous state.
In asynchronous state, setting bit FMR0.FRS induces the synchronizer to lock onto
the next available framing candidate if there is one. At the same time the internal
framing pattern memory will be cleared and other possible framing candidates are
lost.
pattern are correctly found independent of the occurence of CRC6 errors. If only one
or two consecutive multiframe pattern were detected the QuadFALC will stay in the
asynchronous state, searching for a possible additionally available framing pattern.
This procedure will be repeated until the framer has found three consecutive
multiframe pattern in a row.
multiple framing pattern candidates step by step. I.e. if in synchronous state the CRC
error counter indicates that the synchronization might have been based on an alias
framing pattern, setting of FMR0.FRS will lead to synchronization on the next
candidate available. However, only the previously assumed candidate will discarded
in the internal framing pattern memory. The latter procedure can be repeated until the
framer has locked on the right pattern (no extensive CRC errors).
The synchronizer will be completely reset and initiates a new frame search, if there is
no multiframing found. In this case bit FSR0.FSRF toggles.
Synchronization is achieved when framing pattern are correctly found and the CRC6
checksum is received without an error. If the CRC6 check failed on the assumed
framing pattern the QuadFALC will stay in the asynchronous state, searching for a
possible available framing pattern. This procedure will be repeated until the framer
has locked on the right pattern. This automatic synchronization mode has been added
in order to reduce the microprocessor load.
253
Functional Description T1 / J1
PEB 22554
09.98