PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 141

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
IXSP …
IXSC …
Global Configuration Register (Read/Write)
Value after RESET: 00
GCR
VIS…
SCI…
7
VIS
0…
1…
Internal Transmit System Frame Sync Pulse
0…
1…
Internal Transmit System Clock
Only applicable if bit GPC1.SMM is cleared. If GPC1.SMM is set
SCLKX1 of channel 1 provides the working clock for all four channels.
0…
1…
Masked Interrupts Visible
0…
1…
Status Change Interrupt
SCI
H
The working clock for the receive system interface is sourced by
The working clock for the receive system interface is sourced
The frame sync pulse for the transmit system interface is
The frame sync pulse for the transmit system interface is
The working clock for the transmit system interface is sourced
The working clock for the transmit system interface is sourced
Masked interrupt status bits are not visible in registers ISR0-4.
Masked interrupt status bits are visible in ISR0-4, but they are
SCLKR of each channel or in receive elastic buffer bypass
mode from the corresponding extracted receive clock RCLK.
internally by DCO-R or in bypass mode by the extracted receive
clock of each channel. SCLKR is ignored.
sourced by SYPX.
internally sourced by the DCO-R circuitry of each channel.
Additionally, the external XMFS signal defines the transmit
multiframe begin. XMFS is enabled or disabled via the
multifunction ports. For correct operation bits CMR2.IXSC /
IRSC must be set. SYPX is ignored.
by SCLKX of each channel.
internally by the working clock of the receive system interface.
SCLKX is ignored.
not visible in registers GIS and CIS.
SES
ECMC
141
Operational Description E1
0
PD
PEB 22554
(x46)
09.98