PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 178

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Interrupt Status Register 3 (Read)
ISR3
All bits are reset when ISR3 is read.
If bit GCR.VIS is set to ‘1’, interrupt statuses in ISR3 may be flagged although they are
masked via register IMR3. However, these masked interrupt statuses neither generate a
signal on INT, nor are visible in register GIS.
ES…
SEC…
LMFA16…
AIS16…
Semiconductor Group
7
ES
Errored Second
This bit is set if at least one enabled interrupt source via ESM is set
during the time interval of one second. Interrupt sources of ESM
register:
LFA = Loss of frame alignment detected (FRS0.LFA)
FER = Framing error received
CER= CRC error received
AIS = Alarm indication signal (FRS0.AIS)
LOS = Loss of signal (FRS0.LOS)
CVE = Code violation detected
SLIP= Receive Slip positive/negative detected
EBE = E- Bit error detected (RSP.RS13/15)
Second Timer
The internal one second timer has expired. The timer is derived from
clock RCLK.
Loss of Multiframe Alignment TS 16
Multiframe alignment of timeslot 16 has been lost if two consecutive
multiframe pattern are not detected or if in 16 consecutive timeslot 16
all bits are reset.
If register GCR.SCI is high this interrupt status bit will be set with
every change of state of FRS1.TS16LFA.
Alarm Indication Signal TS 16 Status Change
The alarm indication signal AIS in timeslot 16 for the 64 kbit/s channel
associated signaling is detected or cleared. A change in bit
FRS1.TS16AIS will set this interrupt. (This bit is set if the incoming TS
16 signal contains less than 4 zeros in each of two consecutive TS16-
multiframe periods.)
SEC
LMFA16
AIS16
178
RA16
Operational Description E1
RSN
0
RSP
PEB 22554
(x6B)
09.98