PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 241

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

• Data Link Access in ESF and F72 Format
Transmit Elastic Buffer
The transmit elastic store with a size of max. 2
temporary store for the PCM data to adapt the system clock (SCLKX) to the internally
generated clock for the transmit data, and to re-translate time-slot structure used in the
system to that of the line side. Its optimal start position is initiated when programming the
transmit time-slot offset values. A difference in the effective data rates of system side
and transmit side may lead to an overflow/underflow of the transmit memory: thus, errors
in data transmission to the remote end may occur. This error condition (transmit slip) is
reported to the microprocessor via interrupt status registers.
The received bit stream from pin XDI is optionally stored in the transmit elastic buffer.
The memory is organized as the receive elastic buffer. Programming of the transmit
buffer size is done by SIC1.XBS1/0 :
• XBS1/0 = 00 : bypass of the transmit elastic buffer
• XBS1/0 = 01 : one frame buffer or 193 bits
• XBS1/0 = 10 : two frame buffer or 386 bits
Semiconductor Group
be ignored. The FS/DL bit is sampled on port XSIG and inserted in the outgoing data
stream. The received CAS multiframe will be inserted frame aligned into the data
stream on XDI. Data sourced by the internal signaling controller will overwrite the
external signaling data.
Internal multiplexing of data and signaling data may be disabled on a per time-slot
basis (Clear Channel Capability). This is also valid when using the internal and
external signaling mode.
The DL-channel protocol is supported as follows:
- access is done on a multiframe basis via registers XDL1-3 or
- HDLC access or transparent transmission (non HDLC mode) from XFIFO
the signaling information stored in the XFIFO will inserted in the DL bits of frame 26 to
72 in F72 format or in every other frame in ESF format. Transmitting may be done on
a multiframe boundary. Operating in HDLC or BOM mode “flags” or “idle” may be
transmitted as interframe timefill.
Maximum of wander amplitude (peak-to-peak): (1 UI = 648 ns )
System interface clocking rate: modulo 2.048 MHz:
Max. wander : 80 UI in channel translation mode 0
Max. wander : 50 UI in channel translation mode 1
System interface clocking rate: modulo 1.544 MHz:
max. wander: 74 UI
average delay after performing a slip: 96 bits
System interface clocking rate: modulo 2.048 MHz:
142 UI in channel translation mode 0
78 UI in channel translation mode 1
241
Functional Description T1 / J1
bit (two -frames) serves as a
PEB 22554
09.98