PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 292

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

XCRC…
Receive Timeslot Register 1-4 (Read/Write)
Value after RESET: 00
RTR1
RTR2
RTR3
RTR4
TS0…TS31…
Semiconductor Group
7
TS16
TS24
TS0
TS8
Transmit CRC ON/OFF
If this bit is set to ‘1’, the CRC checksum will not be generated
internally. It has to be written as the last two bytes in the transmit FIFO
(XFIFO). The transmitted frame will be closed automatically with a
closing flag.
Note: The QuadFALC does not check whether the length of the
Timeslot Register
These bits define the received time-slots on the system highway port
RDO to be extracted. Additionally these registers will control the
RSIGM marker which can be forced high during the respective
time-slots independently of bit CCR1.EITS.
A one in the RTR1-4 bits will sample the corresponding time-slot in
the RFIFO of the signaling controller, if bit CCR1.EITS is set.
Assignments:
SIC2.SSC2 = 0 : ( 32 time-slots / frame )
TS0
SIC2.SSC2 = 1 : ( 24 time-slots / frame )
TS0
0
RFIFO.
1…
RFIFO. Although the idle time-slots can be selected. This function will
only become active, if bits CCR1.EITS is set.
The corresponding time-slot will be forced high on pin RSIGM.
TS17
TS25
TS1
TS9
H
, 00
The corresponding time-slot is not extracted and stored in the
The contents of the selected time-slot will be stored in the
frame, i.e. the number of bytes to be transmitted makes sense
or not.
time-slot 0, . . . TS31
time-slot 0, . . . TS23
H
TS10
TS18
TS26
TS2
, 00
H
, 00
TS19
TS27
TS11
TS3
H
292
TS12
TS20
TS28
TS4
time-slot 31
time-slot 23
Operational Description T1 / J1
TS13
TS21
TS29
TS5
TS14
TS22
TS30
TS6
0
TS15
TS23
TS31
TS7
PEB 22554
(x0C)
(x0D)
(x0E)
(x0F)
09.98