PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 213

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

PEB 22554
Functional Description T1 / J1
Receive Equalization Network
The QuadFALC automatically recovers the signals received on pins RL1/2 in a range of
up to -36 dB. The maximum reachable length with a 22 AWG twisted-pair cable is 2000
m. After Reset the QuadFALC is in „Short Haul“ mode, received signals are recovered up
to -10 dB of cable attenuation. Switching in „Long Haul“ mode is done by setting of
register LIM0.EQON.
The integrated receive equalization network recovers signals with up to -36 dB of cable
attenuation. Noise filters eliminate the higher frequency part of the received signals. The
incoming data is peak detected and sliced at 55% of the peak value to produce the
digital data stream. The received data is then forwarded to the clock & data recovery unit.
Receive Line Attenuation Indication
Status register RES reports the current receive line attenuation in a range from 0 to -36
dB in 25 steps of approximately 1.4 dB each. The least significant 5 bits of this register
indicate the cable attenuation in dB. These 5 bits are only valid in conjunction with the
most significant two bits (RES.EV1/0 = 01) .
Receive Clock and Data Recovery
The analog received signal at port RL1/2 is equalized and then peak-detected to produce
a digital signal. The digital received signal at port RDIP/N is directly forwarded to the
DPLL. The receive clock and data recovery extracts the route clock RCLK from the data
stream received at the RL1/2, RDIP/RDIN or ROID lines and converts the data stream
into a single rail, unipolar bit stream. The clock and data recovery works with the
internally generated high frequency clock based on MCLK. Normally the clock that is
output via pin RCLK is the recovered clock from the signal provided by RL1/2 or RDIP/N
has a duty cycle close to 50 %. The free run frequency is defined by MCLK = 1.544 MHz
in periods with no signal. The intrinsic jitter generated in the absence of any input jitter is
not more than 0.035 UI. In digital bipolar line interface mode the clock and data recovery
will accept only HDB3 coded signals with 50 % duty cycle.
Receive Line Coding
The B8ZS line code or the AMI (ZCS) coding is provided for the data received from the
ternary or the dual rail interface. All code violations that do not correspond to zero
substitution rules will be detected. The detected errors increment the code violation
counter (16 bits length). In case of the optical interface a selection between the NRZ
code and the CMI Code (1T2B) with B8ZS postprocessing is provided. If CMI code
(1T2B) is selected the receive route clock will be recovered from the data stream. The
1T2B decoder does not correct any errors. In case of NRZ coding data will be latched
with the falling edge of pin RCLKI.
The detected errors increment the code violation counter (16 bits length).
Semiconductor Group
213
09.98