PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 166

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

CRC Error Counter 3 (Read)
CEC3L
CEC3H
CE15…CE0…
CE7…CE2…
CE1…CE0…
Semiconductor Group
7
7
CE15
CE7
Multiframe Counter
Change of Frame Alignment Counter
CRC Error Counter (detected at T Ref. Point via Sa6 -Bit)
GCR.ECMC = 0 : If doubleframe format is selected, CEC3H/L has no
function. If CRC-multiframe mode is enabled, CEC3H/L works as SA6
Bit error indication counter (16 bits) which counts the SA6 Bit
sequence 0010 and 0011in every received CRC submultiframe.
Incrementing the counter is only possible in the multiframe
synchronous state FRS0.LMFA = 0.
SA6 Bit sequence: SA61, SA62, SA63, SA64 = 0010 or 0011 where
SA61 is received in frame 1 or 9 in every multiframe. The error
counter will not roll over.
During alarm simulation, the counter is incremented once per
submultiframe up to its saturation.
GCR.ECMC = 1 : This 6 bit counter increments with each multiframe
period in the asynchronous state FRS0.LFA/LMFA =1.
During alarm simulation, the counter is incremented once per
multiframe up to its saturation.
GCR.ECMC = 1 : This 2 bit counter increments with each detected
change of frame / multiframe alignment. The error counter will not roll
over.
During alarm simulation, the counter is incremented once per
multiframe up to its saturation.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCEC3
has to be set. With the rising edge of this bit updating the buffer will
be stopped and the error counter will be reset. Bit DEC.DCEC3 will
automatically be reset with reading the error counter high byte.
166
Operational Description E1
0
0
CE0
CE8
PEB 22554
(x5A)
(x5B)
09.98