PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 327

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

PD…
Errored Second Mask (Read/Write)
Value after RESET: FF
ESM
ESM
Disable Error Counter (Write)
Value after RESET: 00
DEC
DRBD
DCOEC…
DBEC…
Semiconductor Group
7
7
DRBD
LFA
Power Down
Switches the appropriate single FALC(1-4) between power up and
power down mode.
0…
1…
Errored Second Mask
This register functions as an additional mask register for the interrupt
status bit Errored Second (ISR3.ES). A ‘1’ in a bit position of ESM sets
the mask active for the interrupt status.
Disable Receive Buffer Delay
This bit has to be set before reading the register RBD. It will be
automatically reset if RBD has been read.
Disable COFA Event Counter
Disable PRBS Bit Error Counter
Only valid if LCR1.EPRM=1 and FMR1.ECM are reset.
FER
H
H
Power Up
Power Down
All outputs are driven inactive, except the multifunction ports,
which are driven high.
DCOEC
CER
DBEC
AIS
327
DCEC
LOS
Operational Description T1 / J1
DEBC
CVE
DCVC
SLIP
0
0
DFEC
PEB 22554
(x60)
(x47)
09.98