PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 316

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

SCF…
ELT…
LOS1…
Loop Code Register 1 (Read/Write)
Vaue after RESET: 00
LCR1
EPRM…
Semiconductor Group
7
EPRM
XPRBS
11… -22.5 dB
Select Corner Frequency of DCO-R
Setting this bit will reduce the corner frequency of the DCO-R circuit
by the factor of ten to 0.6 Hz.
Note: Reducing the corner frequency of the DCO-R circuitry will
increase the synchronization time before the frequencies are
synchronized.
Enable Loop-Timed
0…
1…
which is synchronized to the extracted receive route clock. In this
configuration the transmit elastic buffer has to be enabled. Refer to
register FMR5.XTM. For correct operation of loop timed the remote
loop (bit LIM1.RL = 0) must be inactive and bit CMR1.DXSS must be
cleared.
Loss of Signal Recovery condition
0…
1…
Enable Pseudo Random Bit Sequence Monitor
0…
1…
H
normal operation
Transmit clock is generated from the clock supplied by MCLK
The LOS alarm will be cleared if the predefined pulse density
(register PCR) is detected during the time interval which is
defined by register PCD.
Additionally to the recovery condition described above a LOS
alarm will only be cleared if the pulse density is fulfilled and no
more than 15 contigious zeros are detected during the recovery
interval. (according to TR-NWT 499).
Pseudo random bit sequence (PRBS) monitor is disabled.
PRBS is enabled. Setting this bit enables incrementing the bit
error counter BEC with each detected PRBS bit error. With any
change of state of the PRBS internal synchronization status an
interrupt ISR3.LLBSC is generated. The current status of the
PRBS synchronizer is indicated by bit FRS1.LLBAD.
LDC1
-->
LDC0
XPM2-0 = 20
316
LAC1
Operational Description T1 / J1
LAC0
H
, 01
H
, 50
FLLB
H
0
LLBP
PEB 22554
(x3B)
09.98