PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 277

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

8.2
The QuadFALC is programmable via a microprocessor interface which enables byte or
word access to all control and status registers.
After RESET the QuadFALC has to be first initialized. General guidelines for initialization
are described in section Initialization.
The status registers are read-only and are continuously updated. Normally, the
processor periodically reads the status registers to analyze the alarm status and
signaling data.
Reset
The QuadFALC is forced to the reset state if a high signal is input at port RES for a
minimum period of 10 s. During RESET the QuadFALC needs an active clock on pin
MCLK. All output stages are tri-stated, all internal flip-flops are reset and most of the
control registers are initialized with default values.
After Reset bit FMR1.PMOD has to be set high and the device needs up to 20 sec to
settle up to the internal clocking. After FMR1.PMOD has been set the configuration
shown in table 28 is initialized.
Table 28
Configuration if Initialized after RESET
Register
FMR0
FMR1
FMR2
SIC1
SIC2,
SIC3
LOOP
FMR4
FMR5
XC0
XC1
Semiconductor Group
Operational Phase
Initiated
Value
00
00
00
00
00
00
00
00
00
00
00
H
H
H
H
H
H
H
H
H
H
H
Meaning
NRZ Coding, No alarm simulation.
PCM 24 mode, 2.048 MBit/s system data rate, no AIS
transmission to remote end or system interface, Payload
Loop off, Channel translation mode 0
2.048 MHz system clocking rate, Rec. Buffer 2 Frames,
Transmit Buffer bypass, Data sampled or transmitted on
the falling edge of SCLKR/X, Automatic freeze signaling,
data is active in the first channel phase,
Channel loop back are disabled.
Remote alarm indication towards remote end disabled.
LFA condition: 2 out of 4/5/6 framing bits,
Non-auto-synchronization mode, F12 multiframing,
internal Bit Robbing Access disabled
The transmit clock-slot offset is cleared.
The transmit time-slot Offset is cleared.
277
Operational Description T1 / J1
PEB 22554
09.98