PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 77

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

• Auto modes
• Error counter
• Status : errored second
Semiconductor Group
- Automatic remote alarm access
If the receiver has lost its synchronization a remote alarm could be sent automatically,
if enabled by bit FMR2.AXRA to the distant end. The remote alarm bit will be
automatically set in the outgoing data stream if the receiver is in asynchronous state
(FRS0.LFA bit is set). In synchronous state the remote alarm bit will be removed.
- Automatic E bit access
By setting bit XSP.AXS status information of received submultiframes is automatically
inserted in E-bit position of the outgoing CRC Multiframe without any further
interventions of the microprocessor.
- Automatic AIS to system interface
In asynchronous state the synchronizer enforces automatically an AIS to the receive
system interface. However, received data can be transparently switched through if bit
FMR2.DAIS is set.
- Automatic clock source switching
In Slave mode (LIM0.MAS = 0) the DCO-R will synchronize to the recovered route
clock. In case of Loss of Signal LOS the DCO-R switches automatically to Master
mode. If bit CMR1.DCS is set automatic switching from RCLK to SYNC may be
disabled.
- Automatic freeze signaling:
Updating of the received signaling information is controlled by the freeze signaling
status. The freeze signaling status is automatically activated if a Loss of Signal, or a
Loss of CAS Multiframe Alignment or a receive slip occures. The internal signaling
buffer RS1-16 is frozen. Optionally automatic freeze signaling may be disabled by
setting bit SIC3.DAF.
The QuadFALC offers six error counters each of them has a length of 16 bit. They
record code violations, framing bit errors, CRC4 bit errors and CRC4 error events
which are flagged in the different SA6 bit combinations or the number of received
multiframes in the asynchronous state or the change of frame alignment (COFA).
Counting of the multiframes in the asyn. state and the COFA parameter is done in a
6 / 2 bit counter and is shared with CEC3L/H. Each of the error counter is buffered.
Updating the buffer is done in two modes:
- one second accumulation
- on demand via handshake with writing to the DEC register
In the one second mode an internal/external one second timer will update these
buffers and reset the counter to accumulate the error events in the next one second
period. The error counter can not overflow. Error events occuring during reset will not
lost.
The QuadFALC supports the error performance monitoring by detecting the following
alarms or error events in the received data:
framing errors , CRC errors , code violations , loss of frame alignment , loss of signal,
77
Functional Description E1
PEB 22554
09.98