PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 289

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

IC0, IC1…
Common Configuration Register 1 (READ/WRITE)
Value after RESET: 00
CCR1
BRM…
EDLX…
EITS…
ITF…
Semiconductor Group
7
0
1
Interrupt Port Configuration
These bits define the function of the interrupt output stage (pin INT):
IOC1
X
0
1
BOM Receive Mode (significant in BOM mode only)
0
1
Enable DL Bit Access via the Transmit FIFO
A one in this bit position enables the internal DL- bit access via the
receive / transmit FIFO of the signaling controller. FMR1.EDL has to
be cleared switching the DL bits, stored in the XFIFO transparently
through the QuadFALC.
Enable Internal Time-Slot 0-31 Signaling
0…
1…
Interframe Time Fill
Determines the idle (= no data to send) state of the transmit data
coming from the signaling controller.
0
1
BRM
H
Internal signaling in time-slots 0-31 defined via registers
Internal signaling in time-slots 0-31 defined via registers
Reference clock at port SYNC is 1.544 / 2.048 MHz
Reference clock at port SYNC is 8 KHz
RTR1-4 or TTR1-4 is disabled.
RTR1-4 or TTR1-4 is enabled.
10 byte packets
Continuous reception
Continuous logical ‘1’ is output
Continuous FLAG sequences are output (‘01111110’ bit
patterns)
EDLX
IOC0
0
1
1
EITS
Function
Open drain output
Push/pull output, active low
Push/pull output, active high
289
ITF
Operational Description T1 / J1
XMFA
RFT1
0
RFT0
PEB 22554
(x09)
09.98