PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 272

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

• Transmit Direction
8.1.3.1 HDLC Data Transmission
In transmit direction 2x32 byte FIFO buffers are provided. After checking the XFIFO
status by polling the bit SIS.XFW or after an interrupt ISR1.XPR (Transmit Pool Ready),
up to 32 bytes may be entered by the CPU to the XFIFO.
The transmission of a frame can be started by issuing a XTF or XHF command via the
command register. If the transmit command does not include an end of message
indication (CMDR.XME), the QuadFALC will repeatedly request for the next data block
by means of a XPR interrupt as soon as no more than 32 bytes are stored in the XFIFO,
i.e. a 32-byte pool is accessible to the CPU.
This process will be repeated until the CPU indicates the end of message per XME
command, after which frame transmission is finished correctly by appending the CRC
and closing flag sequence. Consecutive frames may be share a flag, or may be
transmitted as back-to-back frames, if service of XFIFO is quick enough.
In case no more data is available in the XFIFO prior to the arrival of XME, the
transmission of the frame is terminated with an abort sequence and the CPU is notified
per interrupt ISR1.XDU. The frame may be aborted per software CMDR.SRES.
Semiconductor Group
correctness. If HDLC mode is selected, the limits for ‘Valid Frame’ check are modified
(refer to description of bit RSIS.VFR).
If CCR3.XCRC is set, the CRC checksum is not generated internally. The checksum
has to be provided via the transmit FIFO (XFIFO) as the last two bytes. The
transmitted frame will only be closed automatically with a (closing) flag.
The QuadFALC does not check whether the length of the frame, i.e. the number of
bytes to be transmitted makes sense or not.
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Operational Description T1 / J1
PEB 22554
09.98