PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 210

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

register CIS to identify the requesting channel. The global interrupt status register serves
itself as a pointer to pending interrupt status registers ISR0 -4 for each channel. After
reading the assigned global interrupt status register and the assigned interrupt status
registers ISR0- 4, the pointer in the GIS and CIS registers are cleared or updated if
another interrupt requires service.
If all pending interrupts are acknowledged by reading (CIS and GIS are reset), pin INT
goes inactive.
Updating of interrupt status registers ISR0…4 , GIS and CIS is only prohibited during
read access.
Masked Interrupts Visible in Status Registers
The channel and global interrupt status registers indicates those interrupt status
registers with active interrupt indications.
An additional mode may be selected via bit GCR.VIS.
In this mode, masked interrupt status bits neither generate an interrupt on pin INT nor are
they visible in CIS and GIS, but are displayed in the respective interrupt status
register(s) ISR0..4.
This mode is useful when some interrupt status bits are to be polled in the individual
interrupt status registers.
Notes:
• In the visible mode, all active interrupt status bits, whether the corresponding actual
• All unmasked interrupt statuses are treated as before.
Please note that whenever polling is used, all interrupt status registers concerned have
to be polled individually (no “hierarchical” polling possible), since GIS only contains
information on actually generated - i.e. unmasked-interrupts.
7.3
Identification Register:
Version:
Part Number:
Manufacturer:
In QuadFALC a Test Access Port (TAP) controller is implemented. The essential part of
the TAP is a finite state machine (16 states) controlling the different operational modes
Semiconductor Group
interrupt is masked or not, are reset when the interrupt status register is read. Thus,
when polling of some interrupt status bits is desired, care must be taken that
unmasked interrupts are not lost in the process.
Boundary Scan Interface
1
32 bit
004D
083 H
H
H
210
Functional Description T1 / J1
PEB 22554
09.98