PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 175

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

RDO…
ALLS…
XDU…
XMB…
Semiconductor Group
LCR1.EPRM=0: This bit is set to one, if the LLB actuate signal or the
LLB deactuate signal, resp., is detected over a period of 25 msec with
a bit error rate less than 1/100.
The LLBSC bit is also set to one, if the current detection status is left,
i.e., if the bit error rate exceeds 1/100.
The actual detection status can be read from the RSP.LLBAD and
RSP.LLBDD, resp.
PRBS Status Change
LCR1.EPRM=1: With any change of state of the PRBS synchronizer
this bit will be set. The current status of the PRBS synchronizer is
indicated in RSP.LLBAD.
Receive Data Overflow
This interrupt status indicates that the CPU does not respond quickly
enough to an RPF or RME interrupt and that data in RFIFO has been
lost. Even when this interrupt status is generated, the frame continues
to be received when space in the RFIFO is available again.
Note: Whereas the bit RSIS.RDO in the frame status byte indicates
All Sent
This bit is set if the last bit of the current frame is completely sent out
and XFIFO is empty.
Transmit Data Underrun
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO and no XME was
issued.
Note: Transmitter and XFIFO are reset and deactivated if this
Transmit Multiframe Begin
This bit is set every 2 ms with the beginning of a transmitted
multiframe related to the internal transmit line interface timing.
Just before setting this bit registers XS1-16 are copied in the transmit
whether an overflow occurred when receiving the frame
currently accessed in the RFIFO, the ISR1.RDO interrupt
status is generated as soon as an overflow occurs and does
not necessarily pertain to the frame currently accessed by the
processor.
condition occurs. They are re-activated not before this
interrupt status register has been read. Thus, XDU should not
be masked via register IMR1.
175
Operational Description E1
PEB 22554
09.98