PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 40

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

The receive jitter attenuator works in two different modes:
• Slave mode
• Master mode
The following table shows the clock modes with the corresponding synchronization
sources.
Mode
Master
Master
Slave
Slave
Slave
Slave
Semiconductor Group
In Slave mode (LIM0.MAS = 0) the DCO-R will be synchronized to the recovered
route clock. In case of LOS the DCO-R switches automatically to Master mode. If bit
CMR1.DCS is set automatic switching from RCLK to SYNC is disabled.
In Master mode (LIM0.MAS = 1) the jitter attenuator is in free running mode if no clock
on pin SYNC is supplied. If a c2.048 MHz clock at the SYNC input is applied the
DCO-R will synchronize to this input.
Internal
LOS Active
independent Fixed to
independent 2 MHz
no
no
yes
yes
SYNC
Input
VDD
Fixed to
VDD
2 MHz
Fixed to
VDD
2 MHz
System Clocks generated by DCO-R
DCO-R centered, if CMR2.DCF =0. (CMR2.DCF
should not be set)
Synchronized on SYNC input (external 2 MHz)
Synchronized on Line RCLK1-4 , selected by
CMR1.DRSS1/0
Synchronized on Line RCLK1-4 , selected by
CMR1.DRSS1/0
CMR1.DCS = 0:
DCO-R is centered, if CMR2.DCF = 0.
(CMR2.DCF should not be set)
CMR1.DCS = 1:
Synchronized on Line RCLK1-4, selected by
CMR1.DRSS1/0
CMR1.DCS = 0:
Synchronized on SYNC input
(external 2.048 MHz)
CMR1.DCS = 1:
Synchronized on Line RCLK1-4, selected by
CMR1.DRSS1/0
40
Functional Description E1
PEB 22554
09.98