PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 216

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

The receive jitter attenuator works in two different modes:
• Slave mode
• Master mode
The following table shows the clock modes with the corresponding synchronization
sources.
Mode
Master
Master
Slave
Slave
Slave
Slave
Semiconductor Group
In Slave mode (LIM0.MAS = 0) the DCO1 will be synchronized to the recovered route
clock. In case of LOS the DCO-R switches automatically to Master mode. If bit
CMR1.DCS is set automatic switching from RCLK to SYNC is disabled.
In Master mode (LIM0.MAS = 1) the jitter attenuator is in free running mode if on pin
SYNC no clock is supplied. If a clock with a frequency of 1.544 MHz (LIM1.DCOC = 0)
or 2.048 MHz (LIM1.DCOC = 1) is applied at the SYNC input the DCO-R will
synchronize to this input.
Internal
LOS Active
independent Fixed to
independent 1.544 or
no
no
yes
yes
SYNC
Input
VDD
2.048 MHz
Fixed to
VDD
1.544 or
2.048 MHz
Fixed to
VDD
1.544 or
2.048 MHz
System Clocks
DCO-R centered, if CMR2.DCF =0.
(CMR2.DCF should not be set)
Synchronized on SYNC input (external 1.544 or
2.048MHz)
Synchronized on Line RCLK1-4 , selected by
CMR1.DRSS1/0
Synchronized on Line RCLK1-4 , selected by
CMR1.DRSS1/0
CMR1.DCS = 0:
DCO-R is centered, if CMR2.DCF = 0.
(CMR2.DCF should not be set)
CMR1.DCS = 1:
Synchronized on Line RCLK1-4, selected by
CMR1.DRSS1/0
CMR1.DCS = 0:
Synchronized on SYNC input (external 1.544 or
2.048 MHz)
CMR1.DCS = 1:
Synchronized on Line RCLK1-4, selected by
CMR1.DRSS1/0
216
Functional Description T1 / J1
PEB 22554
09.98