W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 24

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

Figure 1.9 Power Design
1.5
64pin package description
1.5.1 Difference between 100 and 64pin package
Difference
64 pin
100 pin
T0, T1, GATE0, GATE1, T2, T2EX, nINT1, nINT2,
nINT3, FDXLED, COLLED, RXLED, TXLED, PM2,
Deleted pin
-
PM1, PM0, EXTALE, EXTDATAWR, EXTDATARD,
GPIO3[0:7], GPIO2[3:7]
External memory
X
O
PHY mode setting
only use SFR
use SFR or PM pins
GPIO
max 19pin
max 32pin
*Note: In case of 64pin package, the PHY mode is must be set by PHYCONF SFR. So, user must
set the MODE_EN bit to enable the MODE2 ~ 0 bit configuration. Then set the MODE2 ~ 0 value
and reset the PHY controlling the PHY_RSTn bit. After the reset the 64pin package chip will
be successfully initialized and operate properly.
When the user uses the 64pin package chip,
the code below must be executed in chip initialize routine.
For more detailed information about the PHYCONF SFR, please refer to the section 2.5.10
‘New & Extended SFR’.
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Ver. 1.12