W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 43

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
3
There are no tri-state signals.
nINT0/FA6
nINT1/FA7
nINT2/FA8
nINT3/FA9
TCPIPCore
interrupt can be in high or low level priority group by setting or clearing a bit in the IP(0xB8)
and EIP(0xF8) registers. External interrupt pins are activated by a falling edge signal.
Interrupt requests are sampled at the rising edge of the system’s clock.
TCPIPCore
Interrupt
(nINT5)
The functions of interrupt pins are described in the table below. All pins are unidirectional.
The W7100A core is implemented with two levels of interrupt priority control. Each external
Each interrupt vector can be individually enabled or disabled by changing the corresponding
nINT4
TI & RI
INT2F
INT3F
INT4F
INT5F
WDIF
Pin
Flag
TF0
TF1
TF2
IE0
IE1
Interrupt
Low/Falling
Low/Falling
Function
Device pin INT0
Internal, Timer0
Device pin INT1
Internal, Timer1
Internal, UART
Internal, Timer2
Device Pin INT2
Device Pin INT3
Reserved
Interrupt for
TCPIPCore
Internal,
WATCHDOG
Falling
Falling
Falling
Active
Table 3.1 External Interrupt Pin Description
Type
Table 3.2 W7100A Interrupt Summary
I
I
I
I
I
Low/Falling
Low/Falling
Level/Edge
Pu/Pd
Falling
Falling
Falling
Active
-
-
-
-
-
-
-
-
-
-
-
Description
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
Reserved
Interrupt Request Signal for TCPIPCore
Flag Reset
Hardware
Hardware
Hardware
Hardware
Software
Software
Software
Software
Software
Software
Vector
0x0B
0x1B
0x23
0x2B
0x4B
0x5B
0x03
0x13
0x43
0x63
Interrupt
Number
Ver. 1.12
11
12
0
1
2
3
4
5
8
9
Natural
Priority
10
11
1
2
3
4
5
6
7
8
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