W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 39

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
2.5.9 Stack Pointer
space.
decremented after data is popped in POP, RET, and RETI executions. In other words, the Stack
pointers always points to the last valid stack byte.
2.5.10 New & Extended SFR
The W7100A has an 8-bit stack pointer called SP(0x81) and is located in the internal RAM
This pointer is incremented before data is stored in PUSH and CALL executions, and
PHY_IND(0xEF): PHY indicator register, shows the current state of internal PHY in W7100A.
Note:
ISPID(0xF1) : ID Register for ISP.
ISPADDR16(0xF2) : 16bit Address Register for ISP
ISPDATA(0xF4) : Data Register for ISP.
CKCBK(0xF5) : CKCON Backup Register.
DPX0BK(0xF6) : DPX0 Backup Register.
DPX1BK(0xF7) : DPX1 Backup Register.
DPSBK(0xF9) : DPX Backup Register.
RAMBA16(0xFA) : RAM Base Address Register.
RAMEA16(0xFC) : RAM End Address Register.
PHYCONF (0xFE): W7100A PHY operation mode, reset, power down configuration register
Note: PHY_RSTn: Reset the Internal PHY of W7100A, if user want to reset the PHY usi
SP.7
7
7
-
7
SPD
LINK
FDX
6
-
SP.6
6
6
: 0 – Full duplex / 1 – Half duplex
: 0 – 100Mbps / 1 – 10Mbps
: 0 – The link is down / 1 – The link is up
PHY_RSTn
Figure 2.30 Internal PHY Configuration Register
5
SP.5
5
5
Figure 2.28 Stack Pointer Register
Figure 2.29 PHY Status Register
PHY_PWDN
SP.4
4
4
4
PHY_IND (0xEF)
PHYCONF (0xFE)
SP (0x81)
MODE_EN
SP.3
3
3
3
SP.2
FDX
2
MODE2
2
2
SP.1
MODE1
SPD
1
1
1
MODE0
SP.0
Ver. 1.12
LINK
0
0
0
Reset
0x07
Reset
0x00
Reset
0x00
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