W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 86

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
corresponds to a bit in the Interrupt Register2 (IR2). If an interrupt mask bit is set, an
interrupt will be issued whenever the corresponding bit in the IR2 is set. If the bit of IMR is
set as ‘0’, corresponding interrupt will not be triggered by the enabled bit in the IR2.
which has a value of 2000 (0x07D0).
Bit
4
3
2
1
0
IMR (Interrupt Mask Register) [R/W] [0xFE0016] [0x00]
The Interrupt Mask Register is used for masking interrupts. Each interrupt mask bit
RTR (Retry Time-period Register) [R/W] [0xFE0017 – 0xFE0018] [0x07D0]
This register sets the period of timeout. Value 1 means 100us. The default timeout is 200ms
Re-transmission will occur if there is no response or response is delayed from the remote
5
7
6
5
4
3
2
1
0
S7_INT
7
Ex) For 400ms configuration, set as 4000(0x0FA0)
Reserved
Reserved
Reserved
Reserved
Reserved
PPPoE
Symbol
S7_INT
S6_INT
S5_INT
S4_INT
S3_INT
S2_INT
S1_INT
S0_INT
S6_INT
0xFE0017
6
destination IP address is transmitted during a UDP data transmission. The
UNREACH bit will be set as ‘1’. This bit can be cleared to ‘0’ by writing ‘1’
to this bit.
PPPoE Connection Close
In the PPPoE Mode, ‘1’ is set if the PPPoE connection is closed. This bit can
be cleared to ‘0’ by writing ‘1’ to this bit.
Reserved
Reserved
Reserved
Reserved
Reserved
0x0F
IR(S7_INT) Interrupt Mask
IR(S6_INT) Interrupt Mask
IR(S5_INT) Interrupt Mask
IR(S4_INT) Interrupt Mask
IR(S3_INT) Interrupt Mask
IR(S2_INT) Interrupt Mask
IR(S1_INT) Interrupt Mask
IR(S0_INT) Interrupt Mask
S5_INT
5
S4_INT
0xFE0018
0xA0
4
S3_INT
3
Description
S2_INT
2
S1_INT
Ver. 1.12
1
S0_INT
0
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